搜索资源列表
proc
- vhdl processor,5 commands,memory,testbench
venomgen
- venomgen - C source code of VHDL code generator for CRC, BCH and RS encoder -venomgen- C source code of VHDL code generator for CRC, BCH and RS encoder * polynomials can be entered via command line * variable bus width * automatic testbench
memoryarray
- 由VHDL撰写的两记忆体转置程序，内含testbench与转置源码。-VHDL written by the two memory migration procedures, includes testbench and migration source.
des
- des解密加密的verilog源代码其中包含有测试源代码，仿真结果图-verilog des decrypt encrypted source code which includes testing the source code, Simulation results
counter
- 计数器的VHDL源码及其对于的仿真Testbench 文件的编写-VHDL Code about counter for the "Simple Test Bench" example VHDL Code about adder for the "Simple Test Bench" example
VHDL_io
- 基于VHDL的Testbench读取文件的编写的PDF教程文件，很有用-VHDL Code text_io for the "Simple Test Bench" example VHDL Code about text_io for the "Simple Test Bench" example
fortestbench
- 基于VHDL的Testbench读取文件的编写的PDF教程文件，很有用-VHDL Code text_io for the "Simple Test Bench" example VHDL Code about text_io for the "Simple Test Bench" example
arm9verilog
- AMBA AHB verilog Source code
elevator_controller
- vhdl elevator controller with testbench
code
- 一个基于fpga的简单的实时心电检测系统，包括与pc通讯和qrs检测两部分-A simple fpga-based real-time ECG detection system, including communication with the pc and qrs detection of two parts
uart2bus_latest.tar
- 文档详尽、已验证的UART工程，含有testbench文件。采用VHDL、Verilog语言编写。-Detailed documentation, has proven UART works with testbench file. Using VHDL, Verilog language.
VHDLTESTBENCH
- 本文档对编写vhdl的testbench具有很大的参考价值，偶那个多方面考虑的-The preparation of this document, the testbench vhdl of great reference value, even considering that many
AES_enc_core_tb
- this code discribers testbench for aes algorithm. it is written by .vhdl
ALU
- VHDL实现ALU的源代码，并且提供了一个详细的testbench-ALU VHDL source code implementation, and provides a detailed testbench
VHDL_Somador8Bits
- * FullAdder implementation in VHDL with respectives signals: a, b : in std_logic_vector (7 downto 0) soma : out std_logic_vector (7 downto 0) ci : in std_logic co : out std_logic overflow : out std_logic negativo : out std_logic
ReadFsm
- VHDL小程序，read FSM。可以作为VHDL一次作业使用。包含测试文档testbench。-VHDL applet, read FSM. A job can be used as a VHDL。VHDL code and testbench.
decoder
- It is a simple decoder created using vhdl in xilinx ise.It will helpful for beginners to create deocder using this.testbench for simulation is also created.
Multiplieur-signe
- VHDL code of a signed mixer with a testbench !
74serie-code
- 74系列的源代码 里面还包含了testbench和详细的代码说明-Prepared by flash controller vhdL source code. Contains testbench. Programming Language:VHDL, Tags:VHDL-FPGA-Verilog,
8051_latest.tar
- 8051 Rev 0.2 OpenCores VHDL core with testbench